In the design of semiconductor integrated circuits, it is very important to consider variations in device characteristics (device mismatch) such as Vt (threshold voltage) for a given circuit design, in order to achieve circuit robustness and obtain high manufacturing functional yields for such devices. The matching of device characteristics is particularly critical for the design of analog and mixed-signal circuits, including, but not limited to, differential amplifiers, current mirrors, digital-to-analog converters (DAC), bandgap reference circuits, etc., where relatively small device mismatches can significantly reduce the efficiency or operability of such circuits for a given application.
In general, variations in device characteristics can result from variations in a manufacturing process (process variations) which affect some or all N-doped or P-doped elements of a circuit depending on, e.g., the orientation, geometry and/or location of a device. For example, when manufacturing a semiconductor chip, variations in device characteristics can result from variations in mask dimensions (which causes geometry variations), variations in material properties of wafers, resists, etc., variations in the manufacturing equipment and environment (e.g., lens aberrations, flow turbulence, oven temperature, etc.) and variations in process settings (implant dose, diffusion time, focus, exposure energy, etc.).
Moreover, two identical adjacent devices may behave differently for various reasons. For example, variations in Vt between neighboring transistors can result from fluctuations in number and position of dopant atoms or randomness in line edge roughness of devices. Further, layout asymmetry, pattern density difference variations, and oxidation rate difference due to stress from isolation, all contribute to device mismatch to a certain degree. These mismatches result in different threshold voltages, different current flows, different carrier mobility, and different trigger points. Another source of mismatch is the known “well proximity effect” due to dopants being scattered along the n-well or p-well sidewalls and corners resulting in a non-uniform doping profile. Indeed, depending on the distance between the device and the edge of the well, the difference in threshold voltage could be as much as 800 mV within a distance of 3 microns.
It is known that larger devices can tolerate more threshold mismatch than the smaller devices. Indeed, process mismatch due to lithographic patterning, ion implantation, chemical-mechanical polishing, oxidation, or CVD deposition, makes smaller devices with short channel lengths especially prone to device mismatch problem. On the other hand, although larger devices are not as sensitive to threshold mismatch, their capacitive loading makes them unsuitable for high-frequency operations. Furthermore, larger devices consume more chip area and more power, which increases the cost.